Contemporary integrated circuits (ICs) include collections of interconnected electronic circuits embodied in semiconductor structures formed during processing of a silicon substrate wafer. The formation of a particular IC can require several hundred discrete complex processing steps within a fab, and is carefully controlled and monitored to ensure a high yield of good die for any particular wafer being processed. With all other things being equal, from a device performance perspective, interconnections between distinct logical circuit areas should be as short as possible. In this way, such characteristics as yield, device density, device speed, capacitive delays, power dissipation, signal attenuation, to name a few, are all enhanced. One way to reduce interconnect distance, of course, is to simply create all the logical circuit areas from the same silicon wafer. This approach, however, suffers from extremely high processing costs, and very poor yield. This is because it is fairly well known in the industry that the expected yield of an individual die during any process is inversely proportional to the physical area occupied by such die. Thus, with all things being equal, from a processing perspective, it is much more preferable to have smaller die embodying smaller blocks of logical circuits. This manufacturing reality operates in direct opposition to the general device performance rule mentioned earlier, and each manufacturer typically engineers a a suitable cost/performance compromise for the part in question.
Regardless of the resulting size of the die, or how many circuits are actually embodied in the final die, it is still necessary to communicate with other circuits outside the distinct silicon area embodying such IC. To do this, some type of interconnect is formed which electrically couples signals directly from the IC and transmits them to the outside world (and vice-versa). Interconnects come in many different shapes and sizes, varying from wire bonding, tape automated bonding (TAB) and controlled collapse chip connection (C4). A variety of packagings for encapsulating die and interconnects are also known in the art, such as DIP, CERDIP, SOJ, SOP, TSOP, PQFP, LDCC, PLCC, CLCC, PPGA, CPGA, BGA and SBA to name a few.
Again, however, with all things being equal, an interconnect/packaging combination that is minimal in size is preferred, and that is why so-called chip scale varieties, including “flip chip” types are becoming increasingly popular. Flip chip packaging is well-known in the art, and is described at length in a textbook by John H. Lau entitled “Flip Chip Technologies” (McGraw-Hill 1995). Examples of such types of packaging can also be found in U.S. patent literature, including in U.S. Pat. Nos. 4,930,216 and 4,984,358, which are incorporated by reference herein.
One advantage of this type of packaging is the fact that multiple chips can be assembled in a “stack” fashion, which results in a higher density of circuits, and improved performance because of the short interconnects. Processes for forming the solder bumps on the bottom of a chip scale package for interconnecting other packages are also well-known. One example is further described in a textbook titled “Semiconductor Packaging—A Multi-disciplinary Approach” by Hanneman et al., at pp. 391–395, and such description is hereby incorporated by reference. Other techniques for creating high density circuits include attempts to interconnect entire wafers to other wafers in a stack fashion, as illustrated generally in U.S. Pat. No. 5,229,647.
A typical flip chip type package 100 known in the art is depicted in FIG. 1. It can be seen here that chip package 100 includes a number of bonding pads 110, which are located in a pad area 115 surrounding die (chip) area 120. A total area 130 for package 100 can be seen to be comprised of two distinct sub-areas, therefore, including bonding pad area 115, and die area 120. Again, for a whole number of reasons, including throughput, productivity, cost, and performance considerations, the size of bonding pads 110, and thus area 115, should be kept small compared to the area of chip area 120. However, there is a limit to how small this area can become using conventional processes, because the pads have to be large enough to accommodate a wire bond, or a flip chip type solder bump. Thus, there is inevitably a large amount of surface area, otherwise usable for forming electronic circuits, that is wasted in a chip scale type package as shown in FIG. 1.
Another well-known technique in the art for increasing circuit density within a chip is accomplished by forming holes and/or vias in the substrate of the chip. U.S. Pat. No. 3,962,052 discloses how such holes can created with increased precision by masking both the front and back of the substrate, and doping the exposed areas. In this manner, an etching step can create holes with nearly vertical sidewalls. U.S. Pat. No. 4,348,253 explains that, to avoid the additional registration problem associated with masking both sides of the wafer, a laser hole can be used to create such via holes. The vias, appear to be limited to connecting any circuits to a groundplane, however (as evidenced by the single metallization layer shown at the backside of the substrate) and not for connecting such circuits to another circuit (or set of circuits). In U.S. Pat. No. 4,808,273 additional details are provided for an improved process of electroplating the resulting vias in such substrates. In this reference, the various active elements, bonding pads and metal interconnects are first formed, and then holes are made through the bottom of the substrate to contact the metal bonding pads. It is apparent that this approach, too, is commercially impractical for conventional processing because the fabricating steps are complicated. Another approach for creating via holes in a substrate using a so-called “back-lapping” technique is discussed in U.S. Pat. No. 4,978,639. In this approach, apertures are opened in desired areas of the substrate, using reactive ion etching, but they do not extend all the way through the wafer. A later grinding step is then used to remove enough of the backside of wafer to expose the apertures, creating the vias. Since the masking, etch steps all take place on the front of the wafer, this avoids the backside registration problem. The backside is then completely metallized, and thereafter this layer serves to bridge and form a large ground plane between components within the chip. A similar grinding process is disclosed in U.S. Pat. No. 5,037,782 for the same purpose.
An example of a “stacked” circuit structure using plated holes is illustrated in U.S. Pat. No. 5,682,062. By placing vias in areas where traditional bond pads are found, a number of chips can be stacked on top of each other in a dense form factor.
The aforementioned U.S. patent references, including those describing the various methods that can be used for creating, shaping, and filling holes and vias in substrates, are hereby incorporated by reference. None of the above references, nonetheless, appear to address the problem of how to optimize the usable chip surface area, or how to minimize interconnect areas required to contact other chips. While certain patents issued to Tessera, Inc. are directed generally to this problem (see e.g., U.S. Pat. Nos. 5,148,265; 5,148,266; 5,258,330; and 5,548,091—all of which are hereby incorporated by reference) the solution they proposed involves what is conventionally known as an “interposer,” and the manufacturing operations required to implement this flexible intervening layer (between surface contacts and a ball grid array) are extremely complex.
It is apparent that as chip die sizes become smaller, the design of interconnect areas, including pad shape, size, and placement will become more and more critical, and, at one point, will probably be the limiting factor in chip scale packaging. Thus, this problem needs to be solved in a cost effective manner.
A related problem in semiconductor manufacturing is the fact that at least some portion of the interconnect/packaging operations take place within the main fabrication facility, and this is non-optimal for a number of reasons. First, it is not cost effective, because in general fab space is extremely limited, and equipment, labor and overhead costs are quite high in that environment. Second, if packaging/interconnect processing steps are set up as part of the normal manufacturing cycle within the fab, they can impact wafer throughput (cycle time) considerably, because they are typically slow operations. Thus, it would be much more desirable to perform only those absolutely necessary critical operations within the special environment provided within the fab. Similarly, if packaging operations could somehow be accomplished before normal wafer processing operations were undertaken, this would also reduce cycle time significantly. In fact, if this were possible, a wafer fab facility could be operated with more efficiency, lower cost, and higher throughput.